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78p2241b e3/ds3/sts-1 transceiver novemb er 20 0 1 description the 78p2 241 b is a line interface tran sceive r ic for e3, ds3, st s-1, na t3 and atm ap plicatio ns. it inclu d e s clo ck re covery and tran smitter pulse sha p ing fun c tions for a p p licatio ns u s ing 75 -ohm coaxial ca ble at distan ce s up to 1100 feet. these appli c ation s i n clu de dsl a ms, digital multiplexers, sonet ad d / dro p multi p l e xers, pdh equi pme n t, ds3 to fib e r opti c an d microwave modem s a nd atm wan a c ce ss fo r route r s a nd switch es. the re ceive r re covers cl ock a n d data from a b3zs or hdb3 co d ed ami sign al. it can co mpen sate for over 12db of cable a n d 6db of flat loss. the tran smitter gene rate s a sig nal th at meets the stand ard pul se sha pe requi reme nts. the 28 -pin p l cc 78p22 4 1 b is pi n a n d fun c tion ally com patible to the 78p7 2 0 0l an d the 7 8 p224 1 (2 8 plcc versi o n). the 78p 2241b in the 48-pi n tqf p is pin co mp atible with the 78p22 41 in the sam e packa ge. t o the 7 8 p720 0l fun c tion ali t y, it adds a b3zs/hdb3 ende c, line c ode violati on dete c tor, loop -ba c k an d clo c k pol a r ity sele ction as well a s ability to receive a dsx3 monitor signal. the line cod e violatio n dete c to r has be en a dded to the 78p22 41 fun c tionality. the 78p22 4 1 b is ma nuf actu red in a n adva n ced bicmos pro c e ss a nd o perates at b o th 5v and 3.3 v powe r sup p ly voltages. it con s um es le ss th an 110 ma of su pply cu rre nt. feat ures ? single chip transmit a nd receiv e interfac e for e3, ds3 and sts-1 applic ations. ? interface to 75 ohm co a x ial cable o v er 1100 fee t at sp eed s up to 51.84 mbps. ? compliant w i th ansi t1.102 -19 93, telcordia g r - 4 99 -c ore a n d gr -2 5 3 - c o r e, it u - t g.703, g.82 3 for jitter toleranc e, and g.775 for loss of si g n a l . ? compliant w i th atm fo rum af-phy - 0034 (e3 public uni) a nd af-ph y -0054 (ds3 publ ic uni). ? easily interfaced to at m framer ics such as pmc 734 5 , 7346 qjet a n d 7321. ? unique cloc k re cov e r y r e quires no r e fer e nc e clock or cr y s tal oscillator. ? rec e iv e ds3-high and dsx3 monitor signals ? includes dia gnostic loo p -ba ck for ami and digital signals. ? includes a s e lectable b3 zs/hdb3 endec. ? pin compatible to 78p7 200 (2 8-le ad plcc) and 78p2 241 . ? 28-le ad plcc and 48 -lea d tqfp pack ages ? 3.3 or 5 v operation, icc<11 0ma ? input circ uit w o r ks either tr ans f o r mer or cap acitor c o upled ? line-co d e v i olation dete ctor blo c k dia g r a m pulse shaper clock recovery adaptive equalizer data slicer los linn linp loutn loutp tpos lpbk lf signal detector tneg b3zs / hdb3 decoder b3zs / hdb3 encoder tclk rclk rpos rneg biasing rfo lpbk mo n lbo txen
78p2241b e3/ds3/sts-1 transceiver fu nctio n a l desc ription the 78p2 2 4 1 b is a sin g le chi p line interface ic desi gne d to wo rk with a 51.84 mbit/s sts-1, 44.73 6 mbit/s ds 3 o r 34.3 68 m b it/s e3 si gnal. the re ceive r re covers clo c k, po sitive da ta and n egati v e data from an alternate mark inversi on (ami) sig nal. the ami line input si gn al sho u ld be b3zs or hdb 3 cod ed. the t r an smitter acce pts cl ock, p o sitive, an d n egativ e data and con v erts them in to an ami signal to drive a 75 ? coaxial cable. th e shape of the tran smitted sign al thou g h any ca ble length of 0 to 450 feet com p lie s with the publi s he d tem p la tes of a n s i t1.102 -19 93, tel c ordia t r -nwt-000 4 99 a n d g r - 253 -core, itu-t g.703. the 78p2 241 b is desig ned to wo rk with b3zs or hdb3 cod ed sign als. t h e b3zs or hdb3 en codi ng and d e codin g function s a r e norm a lly in cl uded in th e frame r i c s; ho weve r, a sele ctabl e b3zs/hdb 3 ende c is in cluded in th e 78p22 41b for inte rface to bina ry nrz d a ta. th e 78p22 41b i s de sig ned to ea sily con n e ct to po pula r atm framer ics such a s pmc 734 5 (suni -pdh), pmc 734 6 (q jet) a nd 73 2 1 . operation speed internal bia s gen erators t hat are a d j u sted by th e value of the rfo set the 7 8 p224 1 b pll cent er frequ en cy an d tra n smitter amplitud e fo r the different stand ards. the e# pi n control s the equali z e r re spo n se an d the tran smitter pul se sh ape an d amplitud e. t he follo win g table sh ows the p r op e r set t i ng s. s t a n d a r d r f o value, k ? e# pin settin g e 3 6 . 8 1 l o w d s 3 5 . 2 3 h i g h s t s - 1 4 . 5 3 f l o a t receiver the receiver input can b e either tran sfo r me r-cou p led or cap a cito r cou p led to the ami sign al. in appli c ation s whe r e th e highe st p e rf orma nce a n d isolatio n i s re quired, a 1:1 tran sform e r i s u s e d o n th e re ceiver path . in the appli c ation s , whe r e isolation i s provid ed else whe r e in the circuit, an ac coupli ng can be u s ed. the in puts to the ic are i n tern all y referen c ed to vcc. sin c e t he in put imp e dan ce of the 78p22 41b i s high, the ami line mu st b e terminate d to 75 ? . the input sign al of the 78p224 1b must be limited to a maximum of three con s e c utive zero s usin g a co din g schem e su ch a s b3zs o r hdb3. the ami sign al first enters a sele ctable fixed 20 db amplifier sta ge that co mpen sate s f o r very lo w amplitud e dsx3 monito r sig nal wh en mon pin is held high. t h e si gnal th en enters an e quali z e r an d agc gain stage. the e quali z e r is desi gne d to overcome int e rsymbol i n terferen ce ca use d by l ong cabl e le ngth s . beca use t he e quali z e r is a daptive, the ci rcuit wil l wo rk with a ll sq ua re sh a ped si gnal s su ch a s ds3 high o r 34 mb it/s e3. the varia b le gai n differential a m plifier main tains a con s tant voltage level output reg a rdl e ss of the input v o ltage level. the gain of the amplifie r is adju s ted by detecting the pea k of the sign al and comp ari ng it to a fixed referenc e. outputs of the data comp arato r s are conne cted t o t he clo ck re cov e ry cir c ui t s . the clo ck re cov e ry system em pl oys a pha se locked lo op with an auxiliary freq uen cy-sen siti ve acqui sitio n loop. this system pe rmi t s the loop to indepe nde ntly lock to the frequ en cy an d ph ase of t he in comi ng data strea m without th e need for an external, hi gh p r e c isi on tuned ci rcuits or refe ren c e clo ck sign al. the jitter tol e ra nce of the 78p22 41b meets the req u ire m ent s of telco r dia g r -4 99 -core for categ o ry i equipme n t for ds3 rates an d excee d s th e requirement s of itu-t g.823 for e3 rates. pin 21 mon rec e iv e rang e mvpk mode l o w 9 0 - 8 5 0 ds3/sts-1 n o r m a l h i g h 2 5 - 8 0 ds3 monito r l o w 1 0 4 -12 0 0 e3 norm a l h i g h 2 5 - 8 0 e3 m o n i t o r b3zs/h d b 3 dec o de r the 78p2 2 4 1 b in clud es a sele ctabl e b3zs/hdb3 enco der/ d e c ode r (e nde c). whe n th e en dec pi n is lo w, the ende c is selecte d an d the re ceive r gene rate s a com p o s ite nrz l ogi c d a ta followi ng the b3 z s ( f o r d s 3 / s t s - 1 ) or hd b3 ( f or e3 ) s u bs titu tion cod e s via the rpos/rnrz pin as sho w n bel ow. pin 20 endec rpos/r nr z rne g high pos i tive ami negative ami low nrz data no conn ect 2
78p2241b e3/ds3/sts-1 transceiver function al descrip tion (continue d) the de cod e r al so dete c ts re ceive line cod e violation s (rl c v) and output s a pul se via the rne g/rl cv pin. t h re e dif f erent cla s se s of li ne co de violations a r e detected. 1) too m any ze ro s: m o re than two (three ) con s e c utive zero s in b3zs (hdb3 ) mode . 2) not en oug h zero s b e twe e n bipola r p u lse (b) a nd bipola r violati on pul se (v): (b,v) for b3 zs, (b,v) or (b,0,v) for hdb 3. 3) cod e violatio n: even num ber of bi pola r pul se s (b) dete c ted betwe en bip o l ar violation p u lse s (v ). on the tra n smit side, nrz input data is internally conve r ted t o positive and neg a tive logi c dat a followin g the b3zs (for ds 3/sts-1) o r hdb 3 (for e3 ) sub s titution cod e s. th e nrz data is input to the tpos/tnrz pin as sho w n belo w . pin 20 endec tpos/tnrz tneg high pos i tive ami negative ami l o w n r z d a t a l c v loss of signal should the in put sign al fall belo w a mini mum value for 175 +/ - 75 cy cle s of the re ceive cl ock rclk, the loss of sign al indi cation, lo s goe s lo w. los goe s hig h whe n a valid sign al is re cei v ed at the in p u t for at lea s t 175 +/ - 75 cy cle s of the re ceive cl ock. transmitt er the tra n smitter a c cepts logic l e vel clock (t clk ) , positive d a ta (tpos) a n d neg ative data (t neg ) sign als a nd gene rate s cu rre nt pulses on the lo ut + and l o ut- pins. wh en pro perly co nne cted to a cente r-ta ppe d 1:2 tran sf orme r, an ami pulse i s gene rate d wh ich can d r ive a 75 ? coaxial cable. whe n the recommen ded transfo rme r is use d an d the e# pin is set high, the tra n s mitted pul se sh ape at th e end of the 75 ? terminate d cable of 0 to 450 feet will fit the ds3 template in ansi t1. 102-1993 and telcordi a gr-49 9 -co r e standa rd do cu ments. for sts - 1 a pplication s , t he tran smitte d pul se for a sho r t cabl e meets the requi reme nts of tel c o r di a gr-25 3 -co r e. the e# pin shoul d b e allo wed to float. for e3 appli c ations, the t r a n smitted pul se for a sh ort cabl e meet s the req u irem ents of itu-t g.703. the e# pin is to b e pulled lo w. rc lk/t cl k polarit y rev e rsal: to simplify the interfa c e wi th framer ci rcuitry, rclk and t c lk ca n be inverte d with the ickp pin. pin 10 ickp r c l k t c l k l o w n o r m a l no r m a l f l o a t i n v e r t i n v e r t h i g h n o r m a l i n v e r t loop-b ack modes: the follo win g loop -b ack mode s all o w fo r the diagn osti c te st of th e p c bo ard. t h i s fu nctio n i s cont rolle d by the lpbk pin. pin 28 lp bk loop-b ack low local loop -b a ck (llb) float rem o te loop -back (rlb ) h i g h n o rmal op e r a t i o n local loop-b ack : whe n lpbk is low, the 78p224 1b enters lo ca l loopb ack. in this mod e , the lout +/- tra n smit si gnal s are inte rnally route d to the re ceiver in put circuit. the inco ming lin e receiver ami signal on lin+/- is ignored. with the transmi tter still tied t o the cable, this te st mo de can in dicate a short circuit on th e tran smitter ex ternal co mpo nents or othe r p r obl em i n the tran smit path. rem o te loop -bac k: whe n lpbk pin i s allo we d to flo a t, the 78p 224 1b enters remot e loop ba ck mode. th e rpos/rneg and rclk pins a r e internally tied to the tpos/tneg and t c lk so the sa me a m i sign al that is received b y the frame r is tra n smitted back to th e far end whe r e a bit continui ty test can be performed. line build-o ut: the lin e build-o ut functio n cont rol s the amplitude in ds3 a nd s t s-1 mo de. the sele ct ion of lbo depe nd s on the amount of cable the tran smitter is con n e c ted to . when u s e d with less th an 225 ft of cabl e the lb o pin shoul d be p u lled hig h . with 225ft or mo re cable the lbo pin sho u ld be lo w. 3
78p2241b e3/ds3/sts-1 transceiver pin description: the 28-pin plcc is compatible w i th 78p7200 na me pin tqfp pin plcc t y p e d e s c r i p t i o n lin+ lin- 42 44 1 3 i line input: di fferential ami inputs to the chip. sho u ld be tran sform e r couple d and te rminate d at 75-o h m re si sto r . r c l k 3 3 2 3 o re ceive cl ock: r e c o ver e d r e ceive c l ock. rpos/ rn rz 3 5 2 5 o receiv e p o sitiv e dat a / nrz data : when endec is high, this pin ind i cates r e ception o f a positive ami p u lse on the coax cable. when endec is lo w, it outpu ts nrz data. rne g/ lcv 3 4 2 4 o re ceive nega tive data/lcv: when e nde c is high, this pin indicates re ce ption of a neg ativ e ami pulse on the co ax. wh e n ende c is lo w this pin in di cate s the occurren ce of a line cod e violation . los 39 27 o loss of signa l: logic low in dicate s that receive r si gnal (lin) is belo w the thre sh old leve l for 17575 p e rio d s. rpo s and rne g are fo rced lo w when los =0. lout+ lout- 9 11 9 11 o line out: differe ntial ami output. req u i re s a 2:1 ce n t er tapped tran sforme r an d 30 1 ? re sist o r . tclk 18 16 i tran smitter clock input: th is sig nal is u s ed to latch th e tpos/tnrz and t n eg si gnal s into the 78p224 1. tpos/ tnrz 1 6 1 4 i trans m it pos i tive data / transmit nrz: when endec is high, a logi c one on thi s pi n gene rate s a positive ami pulse on the co ax. this pi n sh ou ld not be high at the same time that tneg is high. when end e c i s lo w, nrz dat a re ce ive d on t h i s pi n i s e n c o d ed in to pos itive an d ne ga tive ami pu lses . t n e g 1 7 1 5 i transmit neg a tive da ta: w hen endec is high, a logic one on this p i n gener ates a negative ami pulse o n the coax. t h is pin should not be high at the sa me time tha t tpos/tnrz is high. whe n endec is low, this pin is ignored. lbo 13 12 i line build -ou t, transmitter: logic lo w used with 22 5ft or more of cable is use d on transmit path. logi c high u s ed with less than 22 5 ft of cable. e# 1 5 1 3 i 3 ds3, e3 and sts-1 sele ct: set low for e# appli c atio ns. set high for ds3, allow to float for sts-1 o p e r ation. fo rme r ly opt! on the 78p720 0. txen 22 18 i tran smitter e nable: when high, ena ble s transmitte r. whe n low, tri-s t ates trans mitter driv ers, lout . this pin wa s called opt@ on 78p7 200. mon 28 21 i dsx3 / e3 monitor sele ct: whe n set hig h , an addition al 20- db gain sta g e is adde d to the re ceive r g a in. this pi n wa s tied to gnd o n the 78p72 0 0 . ickp 10 10 i3 i n v e r t c l o c k p o l a r i t y : w h en low, the polarities of rclk and tc l k are the sa me as those on th e 78 p72 0 0 . wh en se t high , the p o l a rity of t c lk i s i n ve rt ed. wh en al lo wed t o fl o a t, t he p o larities o f bo th rcl k an d tc l k are in ver t ed . lpbk 40 28 i3 loop -b ack select: wh en h i gh, neithe r lo op-ba ck i s activated. whe n allo we d to float rpos, rneg a nd rclk are loope d back onto tp os, tneg a nd tclk. wh en low, lo ut is loope d ba ck onto lin. v c c 5 , 6 , 2 0 , 21,37,38 7,17,26 p powe r suppl y. 4
78p2241b e3/ds3/sts-1 transceiver pin description: th e 28-pin pl cc is compatible w i th 78p7 2 00 (contin ued ) na me pin tqfp pin plcc t y p e d e s c r i p t i o n gnd 1, 3, 4, 7, 8, 12, 14, 19, 23 , 24, 25, 29, 30 , 31, 32, 36, 41 , 43, 45, 46, 47 , 48 2,4,6,8,22 p gro und. con nectin g all ground pi ns to a comm on g r ound plane i s re co mmend ed. rfo 2 5 - a resi stor to gnd set s the operational speed of the chip. rfo = 5.23k for ds3, rf o = 6.81k for e 3 and rfo = 4 . 53k for sts-1. lf1 26 19 - re ceive r pll filter capa cit o r. ende c 2 7 2 0 i enc o der/ d ecoder: when set low, ac tivates b3zs/hdb3 ende c on re ceive r and tra n smitter lo gic signal s. note 1: pin type: i-input; i3-thre e level lo gic inp u t; o-o u tput; p-power supply. advance d data she e t pin assign ment a nd functio n s are subj ect to chan ge. 5
78p2241b e3/ds3/sts-1 transceiver electri cal specificati o ns abs olute maximum ratings opera t ion b e y ond these maximums rating ma y pe rmanen tly d a mage th e d e v i ce. par a mete r r a ting pos i tive s u pply, v cc 6v storage tem p eratu r e -65 to 15 0 ambient ope rating tempe r a t ure -40 to +85 c output pin voltage (l out+, lo ut-) input pin voltage (lin+, lin-) v cc ?2 to v cc + 2 v input pin voltage, all othe r pins v cc + 0 .3 to gnd -0.3 v d c c har acter istic s : ta = - 4 0 supply cu rre n t i cc tran smit an d re ceive all one s, vcc=5 v or 3.3v 7 0 1 1 0 m a supply cu rre n t i cc tran s m i t t e r di sabl e d , txen=0 3 5 m a v il i 0 . 8 v v ih i 2 v i il , i ih i - 1 0 + 1 0 u a v il3 i 3 0 . 5 v z im 3 i 3 i n p u t floating 8 1 0 2 0 k ? v ih3 i 3 v cc -0.5 v i il3 , i ih3 i 3 - 1 00 + 1 00 u a v ol o i ol =-0.1ma 0 . 5 v v oh o i ol =+0. 1 ma v cc -0.5 v 6
78p2241b e3/ds3/sts-1 transceiver e3 ? receiver (rfo = 6. 81k ? , e# is se t lo w ) , receiv e r is trans f or mer-co upled . par a mete r c o nditio n m i n t y p m a x unit peak differen t ial input amplitude, lin+, lin- see note 2 104 1200 mv pk peak differen t ial input amplitude, lin+, lin- monitor m ode m o n = 1 2 5 . 5 8 5 mv pk bit error ratio in the pre s e n ce of an interferin g signal at re ceive input interferin g sig nal po we r 20 db belo w e3 sign al po we r. both are prbs23 (2 23 -1 ) patter n s. 1 0 - 9 rclk rise/fall time trct 2 4 n s rclk peri od, trcf 2 9 . 1 0 n s rclk clo c k d u ty cycle 45 55 % rclk pul se width trc 1 4 . 5 5 n s rpos/rneg data setup time trdps cl =15 p f 7 ns rpos/rneg data hold tim e tr dph cl =15 p f 7 note 2: 104 mv pk equal s 950 mvp at the so urce with 1100 feet of cable (13.2 d b loss). note 3: meet s the jitter tolera nce req u irement of itu-t g.823. note 4: me asure the jitter? s 3db fall off on rclk. in order to me et jitter tran sfer fu nction req u ire m ents with a lowe r band width, a n external jitter attenu ation circuit nee ds to be added. 7
78p2241b e3/ds3/sts-1 transceiver ds3/sts-1 receiver (rfo = 5.23 k ? for ds3 a nd 4.53k ? for sts-1, e# pin is set high or allo w e d to float), input is tran sforme r cou p led par a mete r c o nditio n m i n t y p m a x unit peak differen t ial input amplitude, lin+ a nd lin- (see note 5) mon=0. sign al a t dsx is 3 60-850mvp (see note 6) 9 0 8 5 0 m v p peak differen t ial input amplitude, lin+ a nd lin- mon = 1 2 5 8 0 m v p peak differen t ial input amplitude, lin+ a nd lin- mon = 0. ds3 high (see note 7 ) 90 1200 mvp bit error ratio in the pre s e n ce of an interferi n g signal (is) at lin+,li n - is is a sinu so idal tone, 22. 368 m h z for ds3 or 25.92mhz for s t s-1. data is a prbs15 (2 15 -1) pattern. is power is 10db b e lo w data si gnal power. 1 0 -9 rclk rise/fall time trct cl=25pf 5 ns rclk peri o d trcf ds3 sts-1 2 2 . 3 5 19.29 n s rclk pul se width trc ds3 sts-1 1 2 . 2 4 9.65 n s rpos/rneg data setup ti me trdps cl= 15 pf 7 n s rpos/rneg data hold tim e trpdh cl= 15 pf 7 n s monitor disa bled 64 m v p los thresho l d monitor en ab led 6.4 m v p note 5: signal so urce sho u ld me et ds3 template of ansi-t102.1 993 fi gure 4 and sts-1 templat e of ansi- t102.1 993 fi gure 5, loss cha r a c teri stics of the we7 28a or rg 5 9 b cabl e sh o u ld be b e tter than figu re c2 of ansi-t 102.19 93. note 6: re ceive r ca n handl e up to 450 feet of ca ble loss (5.5d b ) from the dsx cro s s-con nect. note 7: ca se wh ere test sign al is fed di re ctly into re ceive r with fast rise tim e s viol ates ds3 template and norma l m a x i m u m . i n t h i s m o d e n o noise, jitter, or interfe r in g tone impai rm ents will b e a dded. note 8: this i s perfo rmed in digital loop-ba ck m ode. jitte r is suppli ed by a bit error rate teste r an d bit erro rs are me asure d . jitter i s specifie d i n te rms of ui (unit interval) and freq uen cy, is summe d with ds3 prbs15 data throug h 450 feet of cable. 8
78p2241b e3/ds3/sts-1 transceiver timing dia g r a m: receiv e w a v e fo r m s (e3/ds3/st s-1) receive line input (ref) lin+/lin- rclk ickp=low or high rclk ickp=float rpos rneg trdps trdph trdns trdnh trcf trct trct trc trdn 9
78p2241b e3/ds3/sts-1 transceiver receiver j i tter tole rance e3 and ds3 j i tter tolera nce spe c ification s are in itu-t g.823 a nd g.824. the e 3 sp ecifi c atio n is the tight er of the two for fre quen cie s g r e a ter than 2 0 khz. receive jitter toleran c e is not tested duri ng produ ction test. 0. 0 1 0. 1 1 10 10 0 1 . e - 0 5 1. e - 03 1 . e - 0 1 1. e + 01 1. e + 03 1 . e + 0 5 1. e + 07 e3 ds 3 par a mete r c o nditio n m i n n o m m a x u n i t re ceiv e r jit t e r tole ran c e 12 hz to 2.78 hz 10hz to 600 hz 20 khz to 80 0 khz 18 5 0.15 u i 10
78p2241b e3/ds3/sts-1 transceiver receiver j i tter tr an sfer fu nc tion t h e r e c e ive r c l ock re co ve r y lo op filter ch ar ac te r i s t ic s are su ch that the receiver h a s th e follo wing t r ansfe r function. th e co rne r freq ue ncy of the pl l is ap proximatel y 50 khz. re ceive r jitter transfe r fun c tion is not te sted duri ng produ ction test. par a mete r c o nditio n m i n n o m m a x u n i t re ceive r jitte r tran sfer fun c tion belo w 59.6 khz 0.1 db jitter tran sfe r function roll-o ff 20 db/decade -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1. e + 01 1. e + 02 1 . e + 0 3 1 . e + 0 4 1. e + 05 1. e + 06 11
78p2241b e3/ds3/sts-1 transceiver e3 ? trans m itter (rf o = 6.81k ? , e# = low ) par a mete r c o nditio n (see ti min g di ag ram) m i n t y p m a x u n i t tran smitter a m plitude lout+ a nd l o ut - 900 1000 1100 mvp tran smitter a m plitude mi smatch ratio of amp litudes of po sitive and ne gative pulses m e a s ure d at pulse ce nters 0 . 9 5 1 . 0 5 tran smitter width mismat ch ttpl/tthl ratio of widt hs of po sitive and negative pul ses me asure d at pulse half am plitude 0 . 9 5 1 . 0 5 tran smitter p u lse width tt pl, ttpn lout+ a nd l o ut - 14.55 ns tran smit t e r cl oc k dut y cy cl e, ttc/tt c f 4 0 6 0 % trans m itter c l ock period ttcf 2 9 . 1 0 n s tran smitter cl ock pul se wi d t h , ttc 1 4 . 5 5 n s trans m itter c l ock trans i tion time, risi ng an d falling cptt/cntt 0 . 8 3 5 n s data setup time ttdrs 2 . 5 n s data hold time ttdhs 2 . 5 n s 12
78p2241b e3/ds3/sts-1 transceiver ds3/sts-1 transmitte r ( e# = hi gh ) par a mete r c o nditio n m i n t y p m a x unit tran smitter a m plitude lout+ a nd l o ut - 650 800 850 mvp tran smit am plitude with l b o on lout+ a nd l o ut - 700 1300 mvp tran smitter a m plitude mi smatch ratio of ampli t udes of po sit i ve and ne gative pulses m e a s ure d at pulse pea ks. 0 . 9 1 . 1 tran smitter p o we r at 22.368 mhz ds3 only - all ones, 3 k hz band width - 1 . 8 + 5 . 7 d b m tran smitter p o we r at 44.736 mhz ds3 only - all ones, 3 k hz band width - 2 1 . 8 - 1 4 . 3 d b m trans m itter c l ock duty c y c l e, ttc/tt c f 4 0 6 0 % trans m itter c l ock period ttcf d s 3 2 2 . 3 5 n s tran smitter cl ock pe riod ttcf s t s - 1 1 9 . 2 9 n s data setup time ttpds 2 . 5 n s data hold time ttpdh 2 . 5 n s trans m itter c l ock trans i tion time, risi ng an d falling ttcpt, ttcnt 0 . 8 2 4 n s 13
78p2241b e3/ds3/sts-1 transceiver 14 timinging diag r a m: t r ansm it te r wav e forms (e3/ds3/sts-1 ) tclk ickp=high or flo a t tclk ickp=lo w tpos lout+/lout - tneg t r ansmit line output (ref) ttcf ttcpt ttcnt vp vn 0.5 vp 0.5 vn ttc ttpds ttpdh ttnds ttndh ttpl ttnl
78p2241b e3/ds3/sts-1 transceiver e3 transmi t templat e 17 ns 8.65 ns 14.55 ns 12.1 ns 24.5 ns 29.1 ns 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0 0.5 1.0 0.2 15
78p2241b e3/ds3/sts-1 transceiver ds3 trans m it pulse template -0. 2 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 -1 -0. 5 0 0 . 5 1 1 .5 t i m e , un it in t e rv al s no r m a lize d amp litu d e time axis ra nge (ui) normalized amplitude e quation uppe r curv e - 0 . 8 5 < t < -0 .68 0.03 - 0 . 6 8 < t < 0.36 0.03 + 0.5{ 1+sin[ (pi/2)(1+ t /0.34)]} 0 . 3 6 < t < 1. 4 0.08+0.407 e - 1 .84(t - 0.36) lo w e r curv e - 0 . 8 5 < t < -0 .36 -0.03 - . 0 . 3 6 < t < 0.36 -0.03 + 0.5{1 + si n[(pi/2 ) (1 + t/0.18)]} 0 . 3 6 < t < 1 . 4 -0.03 16
78p2241b e3/ds3/sts-1 transceiver sts- 1 transmit pu lse templa te -0. 2 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 -1 -0.5 0 0 .5 1 1 .5 t i me, unit interv als normalized amplitude sts-1 (tr a n s mit template spec s) time axis ra nge (t ) normalized amplitude e quation (a) uppe r curv e - 0 . 8 5 < t < -0 .68 0.03 - 0 . 6 8 < t < 0.26 0.03 + 0.5{ 1+sin[ (pi/2)(1+ t /0.34)]} 0 . 2 6 < t < 1. 4 0.1+0.6 1 e -2.4(t -0.26) lo w e r curv e - 0 . 8 5 < t < -0 .38 -0.03 - 0 . 3 8 < t < 0.36 -0.03 + 0.5{1 + si n[(pi/2 ) (1 + t/0.18)]} 0 . 3 6 < t < 1 . 4 -0.03 17
78p2241b e3/ds3/sts-1 transceiver transmitt er outp ut jitter the tran smit jitter spe c ifica t ion ensure s com p lian c e wi th itu-t g.8 23 and g.82 4, and ansi t1.102 -19 9 for all sup p o r ted rat e s. tra n smit output jitter is not tested du ring p r od uctio n test. t r ans m i t t er out put ji t t e r det e c t or m eas ured j i t t er am pl i t ude 10hz 800k hz 20db / dec ade par a mete r c o nditio n m i n n o m m a x u n i t tran smitter o u tput jitter 10 hz to 800 khz 0.1 ui 18
78p2241b e3/ds3/sts-1 transceiver e3/ds3/sts-1 example circuit note 9: pin n a me s in ( ) de note pin na m e s from 7 8 p7 200. pin num bers refe r to 28 plcc pa ckag e. default setting s used to simulate 7 8 p720 0. note 10: resi stors on t c l k , tneg, tpos are optio nal but re com m end ed. clo ck p u lse sh ap es at the inpu ts to the 78p22 41 b are dep end ent on boa rd l a yout and will dictate the n eed for su ch adde d re si sto r s. note 11. addi ng a se rie s f e rrite be ad o n vcc pi ns may be req u ired for some p c boa rd layo u t. external compone n ts (co m m o n to e3/ds3/ s ts-1) compon e n t t o l e r a n c e v a l u e u n i t re ceive r termination re si stor rt r 1 % 7 5 ? r e c e iver t r an s f or mer t u rn s ra tio t r 3 % 1 : 1 - - - tran smitter t e rmin ation resi stor rtt 1% 301 ? tran smitter t r an sformer t u rn s ratio tt 3% 1:2ct --- external compo n e n ts (dep enda nt on spe e d, nominal v a lue) compon e n t t o l e r a n c e s t s - 1 d s 3 e 3 u n i t loop filte r capa citor clf 10% 0.047 0.047 0.047 f bias resi s t o r r f o 1 % 4 . 5 3 5 . 2 3 6 . 8 1 k ? note 11: adv anced data sheet pin a ssi gnme n t, functions a nd exte rnal comp one nt values a r e subj ect to ch ange. 19
78p2241b e3/ds3/sts-1 transceiver 78p22 41 b replaceme n t for existing 7 8 p720 0 de signs note 12: 78p 7200 com pon ents (su c h a s transmitte r transfo rme r), which a r e n o t shown he re, are not modifie d . compon ent variation for existing 78 p7200 desig n s compo n e n t 7 8 p 7 2 0 0 78p22 41 b r1,r 2 75 ? s h o r t (0 ? ) c 2 8 2 p n o t instal l e d l 2 6 . 8 u n o t instal l e d l 1 0 . 4 7 u n o t instal l e d c 1 1 0 0 0 p n o t instal l e d c 3 0 . 0 1 n o t instal l e d t 1 1 : 2 1 : 1 rt r 422 ? 7 5 ? input filte r c p d 0 . 2 2 u short (0 ? ) rlf 2 100 k ? not installed rlf 1 6.04k ? not installed pll filter clf 1 0 . 2 2 u 0 . 0 4 7 u ds3 301 ? 3 0 1 ? rtt e3 604 ? 3 0 1 ? ds3 5-1 5 p f n o t instal l e d transmitt er ctt e 3 3 p f not i n s t a l l e d power s u pply l v c c 4 . 7 u h short (0 ? ) o r fer r ite bead 20
78p2241b e3/ds3/sts-1 transceiver package pin designations (top vie w ) 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 25 24 23 22 21 20 19 gnd li n- gnd li n+ vcc lbo tp os / t nrz tne g tclk vcc t xen rfo gnd vcc gnd lout+ ickp lout- rpos/rnrz rclk gnd mon rneg/rlcv lf1 78p22 41 b 28-pin plcc mec han ical d raw in g 28-pin plcc pin no. 1 ident. 0.495 (12.573) 0.485 (12.319) 0.495 (12.573) 0.485 (12.319) 0.456 (11.650) 0.450 (11.430) 0.456 (11.650) 0.450 (11.430) 0.075 (1.905) 0.065 (1.651) 0.045 (1.140) 0.020 (0.508) 0.050 (1.270) 0.016 (0.406) 0.020 (0.508) 0.390 (9.906) 0.430 (10.922) 0.165 (4.191) 0.180 (4.572) 21
78p2241b e3/ds3/sts-1 transceiver package pin designations caution: use handling procedures necessary for a static sensitive component. (top vie w ) rneg/rlcv 1 gnd 3 rclk 2 rfo 4 gnd 5 gnd 6 vcc 7 gnd 8 e # 1 7 t p o s / t n r z 1 8 t n e g 1 9 t c l k 2 0 g n d 2 1 v c c 2 2 v c c 2 3 t x e n 2 4 4 7 g n d 4 8 g n d 4 6 g n d 4 5 g n d 4 4 l i n - 4 3 g n d 4 2 l i n + 4 1 g n d 4 0 l p b k 3 8 v c c 3 7 v c c 36 gnd lf1 34 35 rpos/rnrz 33 gnd 32 gnd 31 gnd 30 gnd 29 mon 78p2241b lout- 1 3 gnd 1 4 l b o 1 5 g n d 1 6 gnd 9 10 lout+ 11 ickp 12 g n d 28 27 gnd 26 g n d 25 endec 3 9 l o s vcc 48-pin tqfp (not pin-co mpatible to 78p72 00) 22
78p2241b e3/ds3/sts-1 transceiver mec han ical d raw in g 48-pin tqfp 0.2 (0.008) typ. index 1 8.7 (0.343) 9.3 (0.366) 1.40 (0.055) 1.60 (0.063) 8.7 (0.343) 9.3 (0.366) 0.50 (0.0197) typ. 6.8 (0.267) 7.2 (0.283) 0.0 (0) 0.20 (0.008) 0.60 (0.024) typ. or deri ng info rm atio n part desc ription or der nu mber pac k a ge m a r k 28-pin plcc 78p22 41b-i h 78p22 41b-i h 48-pin tqfp 78p22 41b-ig t 78p22 41b-ig t no responsibility is a ssumed by tdk semic onductor corporation for use of this pr oduc t nor for an y infringements of patents and trademarks or othe r rights of third pa rties resulting from it s use. no license is granted u nder an y p a tent s, patent rights or t r adema r ks o f td k semiconductor corporation, a nd t he compan y re serves the right to make changes in specif icat ions at an y time w i tho u t notice. acc ordingly , th e reader is caution ed to verif y tha t t he dat a sheet is current befo r e pl acing orders. tdk semicondu ctor corp., 2642 michelle dr., tustin, ca 92780, (7 14) 508 -8800, f ax (714) 50 8-88 77 ? tdk semicondu ctor corpo r ation 11/21/01 - rev . d 23

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